1. Field of the Invention
Embodiments of the invention relate generally to nonvolatile memory devices and related methods of operation. More particularly, embodiments of the invention relate to nonvolatile memory devices and methods using resistance materials to store data.
2. Description of Related Art
A variety of nonvolatile memory devices use resistance materials to store data. For example, Phase Change Random Access Memory (PRAM) typically stores data by changing the state of a phase change resistance material between an amorphous state and a crystalline state to discretely modify the resistance of the phase change resistance material. Accordingly, different resistance values of the phase change resistance material can be used to represent logical values “0” and “1” in the PRAM.
Other examples of nonvolatile memory devices using resistance materials include Resistive RAM (RRAM), Ferroelectric RAM (FRAM), and Magnetic RAM (MRAM), to name but a few.
Nonvolatile memory devices such as PRAMs often use a chalcogenide alloy as the phase change resistance material. Accordingly, the logic state of a memory cell in a PRAM can be read by detecting the resistance of the chalcogenide alloy. In selected other nonvolatile memory devices using resistance materials, the logic state of memory cells can be detected by sensing resistance of a Magnetic Tunnel Junction (MTJ) film that varies in accordance with the polarization of a ferroelectric material.
For simplicity of explanation, various concepts will be described below in the context of a nonvolatile memory device in which the phase change resistance material is used to store data. However, those skilled in the art will recognize that the same or similar concepts may be applied to nonvolatile memory devices using other types of resistance materials to store data.
In general, memory cells using phase change resistance materials can be referred to as “phase change memory cells”. Phase change memory cells typically store a logical “0” using a “set state” in which the phase change material is in a crystalline state and therefore has a relatively low resistance value. On the other hand, phase change memory cells store a logical “1” using a “reset state” in which the phase change material is in an amorphous state and therefore has a relatively high resistance.
Data can be written to phase change memory cells by heating and cooling the phase change resistance material to change the material between the amorphous and crystalline states. In general the heating and cooling can be accomplished by applying a “set pulse” or a “reset pulse” to an electrode formed adjacent to the phase change resistance material. For example, to program a logical ‘1’ to a phase change memory cell, the phase change resistance material can be heated to a first temperature greater than a melting temperature of the phase change resistance material and then rapidly cooled to place the phase change resistance material in the amorphous state. On the other hand, to program a logical ‘0’ to the phase change memory cell, the phase change resistance material can be heated to a second temperature greater than a crystallization temperature but lower than the melting temperature, maintained at the second temperature for a predetermined period of time, and then cooled to place the phase change resistance in the crystalline state.
The phase change memory cell can be read by applying a read current to the phase change resistance material and detecting a voltage level of a sensing node whose voltage level varies in accordance with the resistance of the phase change resistance material. The voltage level can be detected, for example, by comparing the voltage level with a reference voltage using a sense amplifier and generating an output signal with a logic level based on the comparison.
PRAMs including phase change memory cells such as those described above typically include a memory cell array in which a plurality of phase change memory cells are arranged, decoders for selecting one or more of the phase change memory cells for a write or read operation, a write driver providing one or more set or reset pulses for write operations, and a sense amplifier providing a read current to the selected phase change memory cell for read operations.
The phase change memory cells generally require more than one different boosting voltage to perform the write and read operations. For example, a read boosting voltage is typically required to generate the read current for the read operation and one or more write boosting voltages are generally required to generate the one or more set or reset pulses for the write operation.
The different boosting voltages are often selectively provided to the phase change memory cells through a switching element. However, where the switching element switches between the different boosting voltages used for the respective read and write operations, complications may arise from capacitative effects on lines providing the different boosting voltages. For example, the capacitative effects may cause a voltage apparent on a node connected to the switching element to undesirably increase. Unfortunately, such effects can negatively impact the performance and reliability of nonvolatile devices.